As an example of a prior art relating to a circuit for detecting motion of a television signal or the like, a motion detecting circuit described in Japanese Patent No. 2585544 is known. FIG. 4 is a block diagram illustrating a structure of the motion detecting circuit that is disclosed in this literature. This motion detecting circuit includes, as shown in FIG. 4, an input terminal 401, a frame memory 402, a subtracter 403, a motion information conversion circuit 404, an integration circuit 405, and an output terminal 406. A television signal that is inputted through the input terminal 401 is inputted to the frame memory 402. The subtracter 403 calculates a difference between input and output of the frame memory 402, i.e., difference between frames (inter-frame difference). Subsequently, the motion information conversion circuit 404 converts the inter-frame difference signal into a signal representing motion. The integration circuit 405 integrates information of motions of the same pixel or peripheral pixels over a limited frame cycle in the past. Through the above operation, the prior art motion detecting circuit can output the motion information from the output terminal 406.
However, because the conventional motion detecting circuit converts the absolute value of the inter-frame difference into the motion information and then integrates the motion information over a predetermined period in the past, when a still picture is connected with another still picture, i.e., when a so-called scene change occurs, a large inter-frame difference is unfavorably calculated. As a result, a motion of the whole image sequence is adversely detected as a large motion, resulting in a degradation in the motion detection accuracy.
Though this degradation does not matter when the period for integrating the motion information is sufficiently long, this degradation causes a serious problem when the integration period is shorter.
Further, since the integration period corresponds to the time that is required for the motion detection, the integration period is desired to be shortened in view of memory reduction.